1. Field of the Invention
The invention relates to the field of displaying auxiliary pictures, for example picture-in-picture (PIP) displays, in wide screen televisions, and in particular, to wide screen televisions which use auxiliary video signal processing circuits designed for conventional televisions for mapping or determining the positions of the auxiliary pictures.
2. Description of the Art
Televisions having a format display ratio of 4:3, often referred to as 4.times.3, are limited in the ways that single and multiple video signal sources can be displayed. Television signal transmissions of commercial broadcasters, except for experimental material, are is broadcast with a 4.times.3 format display ratio. Many viewers find the 4.times.3 display format less pleasing than the wider format display ratio associated with the movies. Televisions with a wide format display ratio provide not only a more pleasing display, but are capable of displaying wide display format signal sources in a corresponding wide display format. Movies "look" like movies, not cropped or distorted versions thereof. The video source need not be cropped, either when converted from film to video, for example with a telecine device, or by processors in the television.
Televisions with a wide display format ratio are also suited to a wide variety of displays for both conventional and wide display format signals, as well as combinations thereof in multiple picture displays. However, the use of a wide display ratio screen entails numerous problems. Changing the display format ratios of multiple signal sources, developing consistent timing signals from asynchronous but simultaneously displayed sources, switching between multiple sources to generate multiple picture displays, and providing high resolution pictures from compressed data signals are general categories of such problems. Such problems are solved in a wide screen television according to this invention. A wide screen television according to various inventive arrangements is capable of providing high resolution, single and multiple picture displays, from single and multiple sources having similar or different format ratios, and with selectable display format ratios.
Televisions with a wide display format ratio can be implemented in television systems displaying video signals both at basic or standard horizontal scanning rates and multiples thereof, as well as by both interlaced and noninterlaced scanning. Standard NTSC video signals, for example, are displayed by interlacing the successive fields of each video frame, each field being generated by a raster scanning operation at a basic or standard horizontal scanning rate of approximately 15,734 Hz. The basic scanning rate for video signals is variously referred to as f.sub.H, 1 f.sub.H, and 1 H. The actual frequency of a 1 f.sub.H signal will vary according to different video standards. In accordance with efforts to improve the picture quality of television apparatus, systems have been developed for displaying video signals progressively, in a noninterlaced fashion. Progressive scanning requires that each displayed frame must be scanned in the same time period allotted for scanning one of the two fields of the interlaced format. Flicker free AA-BB displays require that each field be scanned twice, consecutively. In each case, the horizontal scanning frequency must be twice that of the standard horizontal frequency. The scanning rate for such progressively scanned or flicker free displays is variously referred to as 2 f.sub.H and 2 H. A 2 f.sub.H scanning frequency according to standards in the United States, for example, is approximately 31,468 Hz.
The overlay function in a simultaneous picture display provides timing signals for the display to switch from the large picture to the small picture, and back to the large picture, at the correct time. Both horizontal and vertical timing of the small picture overlay are critical to displaying the small picture. A PIP processor designed for use with 4.times.3 displays is the CPIP chip developed by Thomson Consumer Electronics, Inc. The CPIP chip is described more fully in a publication entitled The CTC 140 Picture in Picture (CPIP) Technical Training Manual, available from Thomson Consumer Electronics, Inc., Indianapolis, Ind. The CPIP chip can be used in such a fashion that the auxiliary video information is stored in a 6 bit Y, U, V, 8:1:1 video RAM field memory. The video RAM holds two fields of video data in a plurality of memory locations. Each memory location holds eight bits of data. In each 8-bit location there is one 6-bit Y (luminance) sample and 2 other bits. These two other bits hold either fast switch data or part of a U or V sample. The fast switch values can be decoded to indicate which type of field was written into video RAM, as either an upper (odd) field, a lower (even) field or no picture (invalid data). The fields occupy spatial positions within the video RAM having boundaries defined by horizontal and vertical addresses. The boundary is defined at those addresses by a change in the fast switch data from no picture to valid field, and vice versa. These transitions in fast switch data define the perimeter of the picture overlay. It will be appreciated that the image aspect ratio of objects in the overlay can be controlled independently of the format display ratio of the overlay itself, for example, 4.times.3 or 16.times.9. The position of the overlay on the screen will be determined by the starting address of the read pointer of the video RAM at the start of the scanning for each field of the main signal. Since there are two fields of data stored in the video RAM, and the entire video RAM is read during the display period, both fields are read during the display scan. The field which is read out of the memory to be displayed is determined by decoding the fast switch data and setting the start position of the read pointer of the video RAM.
A problem arises in those instances when the PIP video processing circuit for the auxiliary video signal embodies an architecture originally intended for use with televisions having conventional format display ratios, that is 4.times.3, such as the CPIP chip described above. Many such processing circuits can be powerful tools for developing multiple picture displays, and their use can simplify and/or accelerate development of wide screen televisions. Indeed, such a 4.times.3 video processing circuit can be programmed to place a PIP insert at many locations, depending on the design. Even in those PIP circuits providing the widest latitude in PIP placement, the placement is horizontally limited within the border of a 4.times.3 display, having a vertical dimension corresponding to the vertical height of the wide screen display. In other words, it is simply not possible to define a position which exceeds the horizontal borders of the 4.times.3 video display map which is defined by the PIP circuit. This display map is a function of the video RAM and the write/read address control which are associated with the PIP circuit. There are two alternatives, but each has a significant disadvantage. One such alternative is to allow the picture to stretch to fill the wide screen display, incurring significant image aspect ratio distortion in both the main picture and in the PIP insert. In another alternative, this horizontal stretching can be avoided by undertaking an asymmetric decimation of the auxiliary video signal to generate the small picture. However, this procedure is extremely difficult because all reduction factors other than three prove to be noninteger processes, and most PIP processors are not capable of any noninteger decimation. Accordingly, PIP inserts would be limited in size, as a practical matter, to a picture 1/3 the size of the original picture. More flexibility in PIP insert size is required in order to implement the many display formats which are possible with a wide screen television.